The present invention relates to the manufacturing in monolithic form of DRAM cells. More specifically, the present invention relates to the manufacturing on a same semiconductive wafer of DRAM cells and of MOS transistors according to a method compatible with a standard CMOS process.
The present invention aims at providing a novel method of simultaneous manufacturing of DRAM cells and of MOS transistors in a same integrated circuit which is relatively simple.
The present invention also aims at providing such a method which enables increasing the density of DRAM cells.
For this purpose, the present invention provides a method of manufacturing DRAM cells in a semiconductor substrate, each including a MOS control transistor and a capacitor, including the steps of:
a) forming first openings in a first insulating layer to partially expose source/drain regions of the control transistors and filling the first openings with a first conductive material;
b) depositing a second insulating layer, forming therein second openings, to partially expose the first openings over contacts with the source/drain regions of the transistors, successively depositing a second conductive material, then a third insulating layer, defining in the third insulating layer and the second conductive material bit line structures of the memory cells, and forming lateral spacers on the sides of the bit lines;
c) depositing a fourth insulating layer;
d) forming in the fourth insulating layer third openings, to partially expose the first openings in contact with the drain/source regions of the transistors;
e) depositing and etching a third conductive material, to cover the walls and the bottom of the third openings, forming a first electrode of the capacitor;
f) conformally depositing a dielectric material forming an insulator of the capacitor; and
g) depositing a third conductive material forming a second electrode of the capacitor.
According to an embodiment of the present invention, before step b) of deposition of the second insulating layer and of formation of the bit line structures, insulating pads are formed above the first openings contacting the source/drain regions of the control transistors.
According to an embodiment of the present invention, step c) of deposition of the fourth insulating layer is performed so that its upper surface is substantially planar.
According to an embodiment of the present invention, the first insulating layer is a multilayer. The lower and upper layers of the multilayer forming the first insulating layer are respectively made of first and second insulating materials selectively etchable with respect to each other. The second insulating layer is also a multilayer. The upper and lower layers of the multilayer forming the second insulating layer are respectively made of first and second insulating materials selectively etchable with respect to each other.
According to an embodiment of the present invention, the insulating pads are formed by deposition of a layer made of a first insulating material. The insulating pads are formed by the deposition of a multilayer, the upper layer of which is made of a first insulating material.
According to an embodiment of the present invention, step a) of forming and filling of the first openings is also performed in a second portion of the substrate to partially expose and contact semiconductive regions.
According to an embodiment of the present invention, the insulating pads are simultaneously formed above the first openings contacting the source/drain regions of the control transistors and the first openings contacting the semiconductive regions.
According to an embodiment of the present invention, the third insulating layer as well as the spacers are made of a first insulating material.
According to an embodiment of the present invention, the fourth and fifth insulating layers are made of a second insulating material.
According to an embodiment of the present invention, the first insulating material is silicon nitride and the second insulating material is silicon oxide.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.